Power5 is a dual-core processor developed by IBM and introduced in fall 2003, in which each of the two processors supports 2-way multithreading and thus forms 4 logical processors. The Power5 chip, which is approx. 400 sq. mm in size, consists of 276 million transistors and is designed in 130 nm technology. It has a clock frequency of 2 GHz.
Each processor core has 120 name registers for calculating integers and floating pointnumbers and eight execution units. They operate at up to 5 instructions per clock cycle and have a computing power of 4 FLOPS per clock cycle. The two processors share an ultra-fast Level 2 cache with a memory capacity of 1.92 megabytes( MB), which has a data throughput of approximately 200 GB/s. The Level 3 cache operates at half the clock frequency of the central processing unit, i.e. at 1 GHz, and is 36 MB in size.
Power5 has a bus width of 256 bits, which can be divided into two unidirectional buses. The clock rate for the bus is around 2 GHz. Power5 uses simultaneous multithreading( SMT) to increase performance.
The Power5, which supports virtualization, is used in iSeries and pSeries servers as well as in blade servers.