burst cycle

To increase the access speed tosemiconductor memories, one optimizes the number of accesses with respect to the address and the stored data.

The burst cycle is specified in a number combination, for example as 4-1-1-1, where the first access to the address comprises 4 cycles of the clock frequency, the following accesses, which concern the data transfer, each last only one cycle.

The burst cycle has evolved with the development of memory devices from formerly 5-5-5 for a DRAM to 5-2-2 for an EDO DRAM in 1995 to 5-1-1 for the PC66, 4-1-1 for the PC100 and 2-2-2 for the PC133.