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fully buffered DIMM (FB-DIMM)

With the FB-DIMM(Fully Buffered Dual Inline Memory Module), the Joint Electron Device Engineering Council ( JEDEC) has specified a memory bus architecture that meets the increased requirements for DRAM technologies. In this architecture, the Advanced Memory Buffer( AMB) forms the central component.

In the new bus architecture, the memory chips are no longer connected in parallel to the System Management Bus( SMBus), but there are point-to-point connections between the memory controller and the first and between the individual memory chips. In contrast to the Registered DIMMs( RDIMM) with a parallel structure, FB-DIMMs have the advantage that the memory can be further expanded even with increasing clock frequencies.

There is an Advanced Memory Buffer (AMB) on each FB-DIMM, which distributes the data between the individual memory chips on the DIMM. The advantage is that the bus access times become independent of the I/O speed of the Dynamic RAMs (DRAM). The AMB chip buffers the data and transfers it to the next DIMM or to the memory controller.

FB-DIMM architecture with AMB chip as buffer

FB-DIMM architecture with AMB chip as buffer

Using FB-DIMM technology, where the data is multiplexed by a factor of 6 and transferred over 24 differential line pairs between the memory controller and the AMB buffer memories. The 24 line pairs are divided into 10 signal lines that transfer the control information from the memory controller to the AMB buffers and 14 line pairs from the AMB buffers back to the memory controller. In the FB-DIMM architecture a total of eight modules can be managed per memory channel. A module can contain up to 36 RAMs. The maximum data rate per I/O pin is 4.8 Gbit/s.

The FB-DIMM technology is designed for the server market and offers the advantage that memories can also be expanded with increasing clock frequencies.

Informations:
Englisch: fully buffered DIMM - FB-DIMM
Updated at: 17.10.2013
#Words: 289
Links: dual inline memory module (DIMM), joint electron device engineering council (JEDEC), memory bus, architecture, dynamic random access memory (DRAM)
Translations: DE
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