pipelined burst SRAM (PBSRAM)

The PBSRAM (Pipelined Burst SRAM) is a Static RAM (SRAM) that is characterized by a particularly short read cycle and is used in conjunction with Pentium CPUs. The read cycle for the four Q-words requires only 6 clock cycles in the sequence 3-1-1-1. In contrast to normal SRAMs, which operate with 9 clock cycles for address decoding (3-2-2), with PBSRAM only the first address is decoded, the following three Q-words are transferred directly to the central processing unit ( CPU). PBSRAMs are used in caches.